The subject matter disclosed herein relates to handling of two-dimensional constraints in layout optimization for integrated circuit (IC) layouts. Specifically, the subject matter disclosed herein relates to solutions for handling both flat and hierarchical two-dimensional constraints in integrated circuit layouts.
Constraints in integrated circuit layouts may include, e.g., line spacing, line width, minimum area, overlap, enclosure, etc. These constraints are typically imposed at the design phase, prior to producing masks used in the manufacture of the IC. While some constraints can be handled using approaches known in the art (e.g., certain one-dimensional constraints), there exist a portion of the overall constraints that cannot be effectively handled.